The present invention relates to a field programmable gate array (FPGA) core interconnect method and/or architecture generally and, more particularly, to an FPGA core interconnect that may enable bug fixes, in-field upgrades, and/or product variations using a common system on a chip (SOC).
One conventional approach for implementing an FPGA core interconnect is to implement an external FPGA chip on the same board as a system on a chip (SOC). Alternately, the FPGA core input/output (I/O) is connected to an I/O of the chip. Another approach is to implement an FPGA core attached to a bus.
The first two conventional methods are limited by speed and size of the I/O of the chip for access to signals to be used in FPGA functions. An FPGA core I/O can be connected to the chip I/O, so that all the FPGA I/Os can have access to all functional chip I/Os. Such an approach has limited usefulness, since the package implements only a few hundred I/O pins. Since there can be hundreds of thousands of gates on the chip, many of the gates would not be accessible with such an approach.
The FPGA core can be attached to an internal bus of the chip. The chip can access the core as if it were part of memory or register address space. Such an approach can provide fast processing of limited functions that can be programmed in the FPGA as the values need to be loaded up, processed, and unloaded. An additional process needs to be implemented to gather the correct signal point values to present to the FPGA process and write back the FPGA processed points. Therefore, it would be desirable to integrate an FPGA core with interconnect architecture on the same chip as another device (e.g., a system on a chip) to improve the utility of the FPGA core.
One aspect of the present invention concerns an apparatus comprising a plurality of register logic circuits, a core circuit, a memory, and a plurality of logic circuits. The register logic circuits may each be configured to generate a first logic signal in response to (i) an input data signal, (ii) a second logic signal, (iii) a first clock signal and (iv) a second clock signal. The core circuit may be configured to generate a plurality of data signals and a first control signal in response to the first logic signals and a second control signal. The memory may be configured to present the second control signal to the core circuit. The logic circuits may each be configured to present the second logic signal in response to the first logic signal and the data signals.
Another aspect of the present invention concerns a method for programming a field programmable gate array (FPGA) comprising the steps of turning a system clock off, turning a scan clock on, forward shifting through a plurality of taps to a selected tap and serially programming one or more first registers from the selected tap.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) add value above simple integration of an FPGA core versus an off-chip FPGA implementation, (ii) allow accessibility to internal signal points, (iii) enable one or more sections of a chip to be accessible to the FPGA core, (iv) allow a scan to minimize the hardware needed to implement an FPGA interconnect, (v) allow a backward scan shift function, (vi) allow a multiplexor to select a data feed from the FPGA, (vii) allow internal FPGA functions to control registers, (viii) implement multiplexors to minimize the hardware needed to implement the FPGA interconnect, (ix) design scales to FPGA size, SOC size and FPGA interconnect fragmentation needs, (x) allow the scan to scan other SOC chips for useful FPGA core inputs, and/or (xi) allow a multiplexor to scan taps, essentially creating a significant amount of inputs for the FPGA functions for a very low hardware cost.